This study investigates the dynamic negative bias temperature instability (NBTI) in PMOS field-effect transistors (FETs) across a temperature range of 77–370 K. PMOS-FETs with varying gate oxide thicknesses are widely employed in integrated circuits. Here, we examine the degradation mechanisms underlying NBTI by analyzing the influence of gate oxide thickness and temperature conditions. Our findings reveal that conventional degradation models fail to adequately explain the non-Arrhenius behavior of NBTI observed at low temperatures. To address this, we propose a mechanism that incorporates both the capture and release dynamics of interface traps (Nit) and oxide traps (Not), highlighting their distinct roles at 77 K. Specifically, we identify that Not dominates in thin-gate oxides at low temperatures, whereas both Nit and Not contribute significantly in thick-gate oxides. Furthermore, the observed behavior at lower temperatures and in thinner gate oxides is qualitatively consistent with the non-radiative multiphonon framework, particularly with respect to charge trapping under reduced thermal activation. At higher temperatures and in thicker oxides, the experimental trends may also be interpreted as involving a possible contribution from gate-side hydrogen release, including hydrogen-related trap formation and field-assisted transport. These results provide a physically grounded framework for interpreting NBTI behavior in PMOS-FETs across a wide temperature range by clarifying the distinct contributions associated with oxide thickness and temperature.

This article analyses the effects of lateral straggling and interface trap on the characteristics of SOI TFETs with an n–p–n configuration in double gate structures using TCAD simulation. The study considers the effects of lateral straggle ( ) in both source and drain regions, along with the impact of acceptor-like and donor-like interface traps having Gaussian distribution. Key analog and RF performance metrics, such as transconductance efficiency ( ), total gate capacitance ( ), gate-to-source capacitance ( ), and gate-to-drain capacitance ( ), cut-off frequency ( ), and intrinsic delay ( under analytical doping profiles are reported. The findings indicate that source-side straggle substantially impairs device performance by widening the tunneling barrier, resulting in diminished and increased , especially at greater σ values. On the other hand, drain-side straggle mostly raises because of stronger coupling, especially in the ambipolar region. The acceptor-like traps lower the performance of the device due to their effect on lowering the carrier density and tunneling rate, while donor-like traps enhance the local electric field intensity, thus increasing the drain current. Based on sensitivity analysis, traps play a critical role within the subthreshold regime. Overall, the work offers insights into the effects of lateral straggle of dopants and interface traps through DC and RF analysis.

This study introduces a self-powered broadband photodetector utilizing a vertical WSe2/MoS2 heterojunction. By optimizing geometric and carrier engineering, the device achieves high-performance, room-temperature operation with zero power consumption. Theoretically, device simulations reveal the underlying physics and limitations of planar configurations, demonstrating that increasing the carrier transport distance from 30 to 80 leads to a 5-fold decrease in responsivity and severe speed degradation. To overcome these theoretically identified limitations, we experimentally developed a vertical architecture utilizing graphene transparent electrodes. Experimentally, operating at zero bias (Vds = 0 V), the vertical device delivers a self-powered responsivity of 31.7 mA W−1 alongside an ultrafast response time of 0.86 under 637 nm illumination. When a bias voltage is applied (Vds = 1 V), the peak responsivity is significantly enhanced to 230 mA W−1. Furthermore, the detector shows specific self-powered capabilities in the 1550 nm telecommunication band, achieving a zero-bias responsivity of 0.84 and an ultralow dark current of . This study establishes a comprehensive framework for designing high-speed, multi-spectral, and energy-efficient two-dimensional optoelectronic systems.

Dark reverse current–voltage (I–V) characteristics as well as various micro-optical imaging modes of a confocal scanning optical microscope such as reverse bias electroluminescence (ReBEL) are utilized for studying the active region of amber high-brightness AlGaInP light-emitting diodes (LEDs). LED images under moderate forward currents exhibit homogeneous light emission from the quadratic chip. Reverse I–V characteristics show avalanche breakdown which enables an estimation of the electric field in the active region of the device as a function of applied bias. ReBEL emission is observed only at locations where avalanche breakthrough current is at its maximum. The electrical heat generated at these locations is also detected by lock-in thermography in the mid-infrared spectral range. A simplified model of electroluminescence (EL) emission is established based on a calculation of local light emission resulting from electron and hole currents. EL images measured under forward currents can be calculated by this model based on a homogeneous injection of carriers from the electrical contacts. However, measured ReBEL images are found to fit well with simulated images only if leakage current of electrons is locally injected from a small region near the chip edge and leakage current of holes is injected via the numerous p-contacts built into the LED. Consequently, comparison of experimental with theoretical ReBEL images allows the local identification of defects responsible for leakage.

To address the sensitivity-selectivity trade-off in conventional tunneling field-effect transistor (TFET) biosensors, this paper proposes a dual-biocavity L-shaped TFET with dual-source regions and dual channels. With a dual-source architecture and a line-tunneling mechanism, the device uses InAlAs blocks to suppress the off-state current, effectively eliminating sensitivity distortion caused by leakage currents. The dual-biocavity design decouples vertical and lateral line-tunneling pathways, enabling differentiated responses to biomolecules with dielectric constants ranging from 2.63 to 12. Simulation results show a threshold-voltage sensitivity (SVth) of 1713 mV and an on-state current sensitivity (SIon) of 3.08 × 1012, outperforming most existing TFET-based sensors. Notably, although SIon degrades with increasing temperature, SVth fluctuates by less than 1% over a 50 K range, exhibiting excellent thermal robustness. Because interface traps significantly degrade switching performance, fabrication requires stringent process control to ensure high interfacial quality. With an optimized biocavity thickness of 4 nm that balances gate controllability and leakage suppression, this study provides a reliable, low-power platform for high-fidelity label-free biosensing, with process tolerance validated for biocavity-thickness variation.

In gate-all-around (GAA) nanosheet field-effect transistors, a higher dielectric constant produces a larger physical high- thickness for a given equivalent oxide thickness, lowering direct tunnelling across the gate that wraps each stacked sheet. This work evaluates 35 gate-dielectric compositions in a four-stack GAA nanosheet FET. Density functional theory-derived dielectric constants ( ) for SiO /SiON/HfO references, doped HfO oxides, and HfMON oxynitrides (M = Al, La, Sr, Ba) were translated into technology computer-aided design material inputs. Across the 35-material set, the intrinsic direct-tunnelling on-state gate current ( ) varies by 15.2 decades, drain-induced barrier lowering varies from 30.8 to 64.6 mV V , and on-state drain current ( ) varies by 9.5%. The latter range is smaller than the change produced by a eV metal-gate work-function shift and illustrates the sensitivity of drive current to gate work function. HfLaON (9% La, 6% N) reduces by 10.3 decades from the HfO value while changing by only 0.20%. The reported values are intrinsic direct-tunnelling estimates. Process-dependent trap conduction can limit the practical leakage reduction.

In this letter, we demonstrate radio frequency (RF) performance of AlGaN/GaN MISHEMTs with Pt/Au gate up to 500 °C, which is the first report of RF operation at 500 °C using a refractory gate metal. The device achieves 1.08 A mm−1, ft of 42.9 GHz, and fmax of 82.4 GHz at room temperature, and retains 0.6 A mm−1, ft of 21 GHz, and fmax of 33.5 GHz at 500 °C. The gate bias for peak ft remains nearly unchanged with temperature, indicating stable RF threshold behavior. These results demonstrate robust high-temperature operation enabled by Pt gate and highlight their potential for extreme-environment RF applications.

While photoluminescence imaging (PLI) is a promising contactless method to detect electrically active defects in Si wafers, improving the visibility of defects requires conventional surface passivation that often consists of ex-situ thin film depositions. This makes the method disruptive, time-consuming and incompatible with high-throughput industrial Si wafer manufacturing processes. Here we study if any of the standard manufacturing-line surface treatments could be used to enhance the photoluminescence signal intensity and thus to reveal the defects of interest. We found that a simple, ex-situ, diluted hydrofluoric acid (HF) treatment applied just before the PLI measurement significantly improves defect visibility. For instance, even very shallow surface scratches (<1 µm) become visible whereas without the HF treatment, microcracks even as deep as 150 µm may not be detectable. Furthermore, we show that performing the HF treatment within a specific timeframe allows the estimation of the defect depth from raw data and the defect distance from either surface if both sides are illuminated. This information is valuable for wafer manufacturers to avoid prematurely discarding wafers that might later undergo surface removal processes. Finally, as a case example, we illustrate how the HF treatment can improve the detection of stacking faults without the need for conventional, disruptive Wright etching.

This work proposes a novel double-gate (DG) junctionless (JL) capacitorless dynamic random access memory (1 T-DRAM) by combining a trench-isolated channel and a high- gate dielectric (TiO ) to improve the performance metrics of the memory cell. The trench-isolated channel architecture design, formed by incorporating SiO filled comb structures within the silicon body, improves charge confinement and reduces recombination, thereby increasing retention time ( ) and sense margin (SM). Comprehensive TCAD simulation results show significant improvements in retention and sensing characteristics. The device achieves a of and SM of at . Also, with an increase in temperature of , it maintains a of and SM of , indicating robust thermal stability. This enhanced electrostatic integrity of the DG JL structure further reduces short channel effects and improves data reliability.

A systematic numerical assessment using a solar cell capacitance simulator is implemented to optimize the device outcome of a p-type Cu2FeSnS4 (CFTS) layer as an absorber, n-type CuAlSe2 (CASe) as an electron transport layer, and n-type fluorine-doped tin oxide (n-FTO) as a window layer with a molybdenum back metal contact of a solar cell. Later, a random forest regression approach was utilized to validate the simulation results and to identify the relative importance of the device features to the photovoltaic (PV) characteristics. A Pearson correlation matrix has been analyzed to pinpoint which layer’s properties should be adjusted carefully to obtain the optimum outcomes. A remarkable power conversion efficiency (PCE) of 27.36% and a fill factor of 85.22% with an open circuit voltage of 0.934 V and a short circuit current density of 34.38 mA cm−2 are attained. It is found that the p-CFTS/n-CASe/n-FTO cell with dimensions of 6 µm/0.1 µm/0.1 µm layer thicknesses, and doping concentrations of 5 × 1019 cm−3/1016 cm−3/1016 cm−3, with an overall defect density of less than 1014 cm−3 are required for such performance. The promising outcomes from numerical and machine learning approaches will eventually provide feasible directions to fabricate high efficiency CFTS based PV cells in the near future.