Defect related disorder during InN growth is a major challenge for high performance electronic and optoelectronic devices. Film quality is often described using reactor specific settings instead of general physical variables. We test whether plasma assisted MOCVD (PA-MOCVD) growth of InN can be described using a single thermodynamic driving force coordinate. We build a driving force coordinate from the process conditions and use it to organize growth kinetics, defect sensitive Raman response, and structural coherence across different growth conditions. A kinetic Monte Carlo (KMC) model with driving force biased incorporation and defect activation events is used to test the proposed mechanism. When plotted against this coordinate, the incorporation rate follows an activated trend with a clear kinetic scale. Raman measurements show a crossover between a defect sparse and a defect rich regime: a disorder activated metric increases rapidly beyond the onset, while an A1-LO control metric stays statistically invariant. This suggests that short range lattice disorder, rather than long range polar coupling, dominates defect activation. X-ray diffraction shows that the out of plane coherence length is similar for samples that share the same driving force, even when their reactor settings differ. The KMC model reproduces the observed exponential trends and the two regimes. A single driving force coordinate brings together growth kinetics, defect activation, and structural coherence in PA-MOCVD InN, and offers a practical way to identify and reach defect sparse growth conditions.

This manuscript proposes a novel extended-channel gate-stacked heterojunction tunnel field-effect transistor, simulated using Synopsys Sentaurus TCAD with relevant physical models. The proposed device incorporates an extended-channel with SiGe as the source material, along with an L-shaped pocket and a dielectric pocket (DP). Device performance is analyzed for varying germanium mole fractions in Si1–xGex at 300 K, where an increase in the mole fraction enhances ION, accompanied by a rise in IOFF. Likewise, structural optimizations include comparison of source materials (Si and Si1–xGex), source doping variations, and evaluation of DP inclusion. The suggested TFET achieves a high ION of 3.52 × 10−4 A µm−1, an excellent ION/IOFF ratio of 2.79 × 1013, and a steep SS of 10.52 mV dec−1 at mf = 0.3, along with an IAMB of 3.46 × 10−17 A µm−1. Notable radio frequency (RF) achievements include a fT of 62.4 GHz, a gain-bandwidth product of 5.78 GHz, and an fmax of 671 GHz, along with a reduced transit time, collectively indicating the high-speed capability of the proposed device and making it well-suited for low-power analog circuits and RF amplification. The device performance is systematically evaluated under interface trap charges with Uniform and Gaussian distributions for varying mole fractions. The analysis indicates that trap-induced degradation affects both ION and IOFF, with IOFF showing a markedly greater degradation compared with the relatively moderate reduction in ION. Additionally, Flicker, Diffusion and Generation–Recombination noise are analyzed up to 1011 Hz in terms of SID. Finally, benchmarking against existing designs demonstrates improved figures of merit, thereby confirming the superior performance of the proposed device.

We calculate the radiative and Auger recombination rates in polar c-plane and nonpolar m-plane InxGa1−xN/GaN quantum wells (QWs) with different alloy compositions x ranging from 0.1 to 0.5. The calculation is based on a full-zone electronic structure description obtained with the linear combination of first-principles (density functional theory with GW corrections) bulk bands approach. The results show that both the radiative and Auger recombination coefficients are higher in nonpolar QWs for all alloy compositions studied. We find that the competition between radiative and Auger recombination cannot explain the experimental findings on the improved performance of m-plane quantum well light emitters, suggesting a significant contribution from another efficiency reduction mechanism, likely not purely intrinsic but related to carrier transport and confinement.

A novel 1200 V planar split-gate 4 H-SiC MOSFET with an enlarged grounded P+-shielding and local N-compensation (PSC-MOS) is proposed and investigated using TCAD simulations for enhanced drain-induced barrier lowering (DIBL) suppression and switching performance. By introducing the N-compensation region adjacent to the P+ shield within the JFET region, depletion-induced current-path constriction is alleviated, thereby strengthening drain-to-channel electrostatic shielding and reducing gate-drain capacitive coupling without an excessive conduction penalty. The N-compensation parameters are optimized by considering the trade-offs among DIBL suppression, conduction capability, and breakdown performance. Demonstrated by TCAD simulation results, compared with the uncompensated LPS-MOS employing the same enlarged P+ shield, the optimized PSC-MOS reduces the specific on-resistance (Ron,sp) and switching loss (Esw) by 39.1% and 23.2%, while increasing the Baliga figure of merit (BFoM) by 58.7%. Compared with the conventional P+-shielded MOSFET (PS-MOS), it reduces the DIBL coefficient (kDIBL) by 17.1%, the high-frequency figure of merit (HF-FoM, Ron,sp × Qgd) by 9.7%, and Esw by 3.2%. These results demonstrate an improved balance among electrostatic control, conduction capability and switching performance.

We present the design and numerical simulation of a top-illuminated Ge/GaAs avalanche photodiode (APD) with a separate absorption, charge, and multiplication structure operating at 1550 nm. The design targets a practical balance between high performance and low manufacturing cost for long-wavelength APDs. Leveraging high carrier mobility and the nearly lattice-matched Ge/GaAs interface, Ge/GaAs APDs provide a path to low-cost, monolithic integration of GaAs with silicon photonic platforms while meeting the demand for high-speed, low-noise photodetectors. Simulations indicate that a 10 μm-diameter device achieves >30 GHz 3-dB bandwidth, a ∼224 GHz gain–bandwidth product, breakdown voltage of approximately −17 V, and low dark current (1.86 μA). These results highlight the strong potential of the Ge/GaAs platform for next-generation high-speed photodetectors.

A new monolithic integration structure of high-side and low-side silicon-carbide (SiC) lateral metal–oxide-semiconductor field-effect transistor (MOSFET) with patterned P-buried layer is proposed. The patterned P-buried layer is achieved by ion implantation on an N-type wafer. It not only contributes to the quality of the P-type layer but also enables superior application of the optimum variation lateral doping technique, leading to optimized device performance. The simulation results show that the high-side device exhibits a breakdown voltage (BV) of 894 V and a specific on-resistance (Ron, sp) of 1.60 mΩ·cm2, while the low-side device achieves a BV of 886 V and a Ron, sp of 1.55 mΩ·cm2, indicating highly matched performance which is crucial for avoiding shoot-through current and optimizing switching performance. With a Baliga Figure of Merit reaching 500 MW cm−2, this work represents a 60.2% enhancement compared to the reported planar SiC lateral MOSFET.

Germanium/silicon–germanium (Ge/SiGe) heterostructures are a promising platform for gate-defined hole spin qubits; however, their practical implementation is often constrained by electrostatic instabilities and inconsistent Ohmic contact quality, which together limit device tunability and functional yield. In this work, we present a systematic engineering approach to mitigate these issues through gate-dielectric interface optimization and a measurement-guided selective post-annealing protocol. First, we demonstrate that replacing atomic-layer-deposited HfO2 with Al2O3 significantly suppresses the rate of charge drift, effectively extending the time scales of stable operation for quantum dot chemical potentials from minutes to extended day-scale time spans, where stability is defined operationally as a drift smaller than half the full width at half maximum of a Coulomb peak over several days. Second, to address the variability in Ohmic contact without compromising the device’s capability to form well-defined quantum dots, we introduce a post-fabrication annealing strategy guided by cryogenic electrical screening. Thermal treatment at 300 C–450 C for 15 min under a N /H ambient reduces the low-temperature contact resistance to below 20 k while preserving the integrity of the electrostatically defined potential wells. By synergistically applying these optimizations, we reproducibly achieve double-quantum-dot charge stability diagrams and integrated charge sensing with an equivalent energy noise level of eV/ at 1 Hz. These results provide a robust and scalable engineering pathway for improving the stability and usability of Ge/SiGe hole quantum-dot devices.

Calculations and measurements of the zero point renormalization (ZPR) energy of the fundamental gap of semiconductors (SCs) have attracted scientific interest for decades. Examination of the thermodynamics of the formation of electron–hole pairs (ehp) in non-degenerate SCs indicates that is proportional to the standard entropy change for this reaction, at temperatures much larger than the Debye temperature . Consequently, if a kinetic compensation effect (KCE) governs the ehp generation process, the ZPR energy should exhibit a coarse-grained correlation with the corresponding enthalpy change . Indeed, non-degenerate, covalent bulk SCs can be grouped such that all members of a given group f will satisfy, on average, a trend that is shown here to hold to a significant extent, with the possible exception of crystals with a wurtzite structure. These observations support the applicability of the KCE to the equilibrium generation–recombination reactions in covalent SCs and insulators. Showing that the is proportional to an observable thermodynamic quantity also clarifies why the ‘bare’ gap energy at absolute zero can be experimentally determined.

A new concept beta-gallium oxide (β-Ga2O3) device—lateral β-Ga2O3/p-NiO heterojunction insulated-gate bipolar transistor (IGBT) is proposed and investigated for the first time via technology computer-aided design simulations. The n-Ga2O3/p-NiO heterojunction in the anode region facilitates efficient hole injection and strong conductivity modulation, thereby effectively enhancing the on-state current density. Nitrogen implantation (NI) beneath the gate is incorporated to form a current blocking layer, which enables reliable enhancement-mode (E-mode) operation. In addition, the p-NiO layer introduced above the drift region, together with the n-Ga2O3 region and the overlying Al2O3 layer, forms a superjunction-like drift region, thereby optimizing the electric field distribution during reverse blocking condition, leading to a significantly improved breakdown voltage (Vbr). Simulation results show that with a drift region length (Ldrift) of 30 μm, the proposed IGBT achieves a breakdown voltage of 15.2 kV and exhibits excellent on-state conduction characteristics. At a gate voltage of 15 V and an on-state voltage of 10 V, the on-state current density of the proposed IGBT is nearly 3 times that of the β-Ga2O3 metal-oxide-semiconductor field-effect transistor with the same drift region length and doping concentration. In summary, this work offers a promising pathway and valuable guidance for the development of high-performance β-Ga2O3 IGBT devices.

In a mesa-isolated diode, the aspect ratio plays a significant role in introducing the Trench MOS barrier Schottky (TMBS) effect, thus incorporating the reduced surface field (RESURF) effect. In this work, first, heterojunction diode structures based on Gallium oxide ( ) and p-type nickel oxide ( ) are designed and analyzed using TCAD simulations. Two layers of p-type of different doping concentrations in heterojunction diode design provide better field management and improved device consistency compared to its single-layer counterpart. based vertical heterojunction diodes are fabricated using sputtered . The designed structure gives a breakdown voltage of 1.32 kV with an ON-resistance ( ) of 6 m cm . The fabricated large-area mesa-isolated multi-finger vertical heterojunction diodes exhibit an absolute forward ON-current ( ) above 1 A and reverse blocking voltage 850 V. The total anode area is 2 while the fingers are 2 mm-long.The carrier concentrations in the 14 -thick top layer and 7.5 -thick bottom layer of are 4–6 and 1.5 , respectively. further increases to 1.5 A at a forward bias of 4–6 V for large-area mesa-free heterojunction diodes. Achieving such a high forward current at low voltages is advantageous for reducing power losses and improving efficiency and stability during diode operation.