With advances in AI and the widespread adoption of NAND Flash technology imposing increasingly stringent performance requirements, conventional erase was unable to provide precise erasing in NAND Flash storage systems. This work proposes a novel cell-level erase scheme called hole pool (HP) erase by integrating the cell-level voltage scheme with the source acceptor doping structure. The technique was evaluated in 3D NAND Flash structures with different numbers of layers, in which stable electric field and charge variation characteristics were obtained, thereby demonstrating its feasibility and applicability to highly stacked architectures. The results showed that the HP erase successfully enabled precise cell-level erase in 3D NAND Flash, which reduced erase operations in unselected cells. Additionally, the optimized erase scheme lowered the required erase voltage, which provided a more efficient approach for erase operations. This highlights a promising direction for the future development of erase technology in highly stacked NAND Flash architectures.

Accurate band offsets are essential for predictive continuum modeling of nanostructures such as quantum wells and quantum dots formed in strained Si/Si Ge and Ge/Si Ge heterostructures. Experimental offset data for these systems remain sparse away from endpoint compositions, which makes composition-dependent design difficult. We use atomistic, first-principles density functional theory to compute valence- and conduction-band offsets across the full range . Random alloying is treated with special quasirandom structures, interface lineup terms are extracted from macroscopically averaged local Kohn–Sham potentials in thick periodic superlattices, valence-band spin–orbit coupling is included through species-resolved Mulliken weights, and conduction-band edges are refined using the screened hybrid Heyd–Scuseria–Ernzerhof functional. The resulting offsets show pronounced composition nonlinearity beyond the linear models explored in previous works, agree with experimental benchmarks, and reproduce the high-Ge slope change in the relaxed-alloy band gap. Analytic fitting expressions are provided for direct use in simulations, facilitating practical design of modern quantum technology devices.

The turn-on speed of gate turn-off (GTO) is a critical performance metric in nanosecond pulse applications. This work analyzes the super-injection effect in heterojunctions and proposes a fast-turn-on SiC heterogeneous GTO thyristor to overcome the insufficient response speed of conventional SiC P-GTOs. Through analysis of asymmetric electron and hole potential barriers, physical insights into injection modulation are revealed numerically. The Ron,diff of a diamond/SiC heterojunction is 2.4 mΩ cm2 at 200 A cm−2, which is 22% lower than that of a SiC homogeneous junction. The hole injection efficiency is raised to above 0.99. Consequently, a diamond/SiC heterogeneous GTO (DH-GTO) raises the accumulated carrier density by about two times via the super-injection effect. The current rise time is shortened to a mere 15 ns under a 8 kV/4 kA and 100 ns pulse. The design achieves a 152% theoretical improvement in di/dt with wide doping tolerance, resulting in a quasi-rectangular pulse waveform. Compared with homogeneous and other heterogeneous GTOs, the DH-GTO demonstrates the most promising static and pulsed performance along with broad doping tolerance. These results provide a novel optimization strategy for improving the turn-on transient of SiC GTOs, thereby advancing nanosecond power pulse technology.

Aluminum nitride (AlN) thin films on silicon substrates hold significant promise for complementary metal-oxide-semiconductor (CMOS)-compatible piezoelectric, acoustic, and electronic devices. However, their crystallinity, stress state, surface morphology, and dielectric response are strongly affected by interfacial mismatch, thermal-expansion mismatch, film thickness, and post-deposition annealing. In this work, we investigate the annealing-induced structural evolution and structure–property correlations of sputtered AlN films on Si(100) and Si(111) substrates, with film thicknesses of 20–1000 nm and annealing temperatures of 700 °C–1000 °C. For both substrate orientations, increasing AlN thickness promotes c-axis-oriented crystallization but gradually deteriorates surface morphology. XRD, Raman, and TEM/HRTEM results indicate the presence of an interfacial SiNx/Si3N4 transition layer, which weakens the direct influence of substrate orientation on AlN crystalline quality. Annealing shifts the AlN(002) diffraction peak toward higher angles, indicating enhanced in-plane tensile stress mainly caused by thermal-expansion mismatch between AlN and Si. Thin films, especially those ⩽100 nm, show more pronounced annealing-induced crystallinity improvement, whereas thicker films ⩾300 nm exhibit relatively stable crystallinity but are more susceptible to crack formation at high annealing temperatures. Dielectric measurements further show that 800 °C annealing improves the effective dielectric response while maintaining low dielectric loss, whereas 1000 °C annealing increases dielectric loss despite a high apparent dielectric constant. These results provide critical insights into the thickness- and annealing-dependent structural evolution of sputtered AlN/Si heterostructures and offer practical guidance for selecting deposition parameters and post-annealing conditions for high-quality AlN films on silicon substrates, thereby paving the way for the development of advanced CMOS-compatible AlN-based devices.

This paper presents a compact model for gate-induced drain leakage-assisted erase transients in metal-gate 3D NAND flash memories. The proposed model incorporates key physical mechanisms, including hole injection, electron back-tunneling, and pure tunneling electron emission. The model is implemented in SPICE to support string-level simulations involving multiple memory cells. Analytical electrostatic solutions are derived using 1-D cylindrical Poisson equations, enabling field-dependent current modeling across the O/N/O stack. The impact of gate work function (WF) on erase performance and speed is systematically investigated. Carrier injection timing analysis via technology computer-aided design (TCAD) reveals asymmetric behavior between hole and electron injection, emphasizing the necessity of modeling both mechanisms. Furthermore, a time-dependent capture ratio is introduced to bridge the discrepancies between TCAD and compact models. The proposed model shows strong consistency with reference TCAD results across various WFs and time scales, offering a physics-based phenomenological framework for circuit-level erase modeling in advanced 3D NAND architectures.

Using admittance spectroscopy, the dispersive transport mobilities of electrons and holes were simultaneously obtained from the distinct carrier transit times (τt) in the molecular beam epitaxy-grown GaAs/AlxGa1−xAs heterojunction-based solar cell device. The negative capacitance effect was attributed to the delayed response of injected carriers under forward-bias space-charge-limited conditions, where different electron- and hole-related transit times appear in different frequency regions of the C-log f characteristics when VF exceeds approximately 1.2 V. For VF < 1.2 V, i.e. below the built-in voltage (Vbi), the activation energy determined from the current density–voltage (J–V) characteristics was attributed to the hole energy barrier associated with the valence-band offset between p+–Al0.82Ga0.18As and p+–GaAs layers. This assignment is consistent with literature-based theoretical band-offset estimates and is also supported by the photoconductivity measurements.

To improve the threshold voltage (Vth) of the enhanced GaN HEMT device, mitigate the risk of false turn–on due to crosstalk between high-side and low-side HEMTs, and decouple the reverse turn-on voltage (VRT) from the gate–source voltage to minimize losses during reverse conduction, this paper introduces a decoupled dual-gate HEMT (DDG-HEMT) device. The DDG-HEMT features a decoupled auxiliary gate on the extended p–GaN region on the source side and employs a clamping mechanism between the main gate and the source, resulting in a substantial increase in the Vth. Based on equivalent circuit model and band diagram analysis, the physical mechanisms of DDG-HEMT are clarified. The research findings indicate that as the thickness of the extended p-GaN region on the source side of the DDG-HEMT increases from 9 nm to 15 nm, the Vth rises from 2.80 V to 4.79 V. Compared to the 1.52 V Vth of C–HEMT, increased by 84.2% and 215.1% respectively. Simultaneously, the transconductance of DDG-HEMT improved by approximately 60% compared to the 40.5 mS mm−1 of C–HEMT devices. Additionally, this paper characterizes dynamic parameters, including gate capacitance and gate charge. The results show that, with the extended p–GaN region thickness of 10 nm on the source side, the gate capacitance measures 384.2 nF cm2, and the gate charge is 4.2 nC. Notably, the DDG-HEMT decouples the VRT from the gate–source voltage, allowing for a high Vth while stabilizing the VRT at 1.20 V across varying gate–source voltages. In practical applications, this capability significantly reduces losses during reverse freewheeling, thereby enhancing overall system efficiency.

This study demonstrates that optimized O2/Ar mixed plasma treatment effectively enhances both electrical performance and hydrogen resistance of indium–gallium–zinc oxide (IGZO) thin-film transistors. At the optimal 4-minute condition, a subthreshold swing of 80 mV dec−1 and hysteresis of 0.07 V were achieved, with the FGA-induced threshold voltage shift (ΔVTH) suppressed from −5.34 V to −0.28 V, confirming substantial hydrogen tolerance improvement. These improvements are attributed to oxygen radical activation promoted by the O2/Ar plasma, which passivates oxygen vacancies and densifies the metal–oxygen–metal bonding network. X-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry analyses attribute this enhancement to the suppression of stable substitutional hydrogen formation via vacancy passivation. Conversely, excessive treatment (10 min) leads to over-oxidation-induced defect states that degrade reliability. These findings establish O2/Ar plasma treatment as a process-compatible strategy for engineering hydrogen-resilient, high-reliability IGZO thin-film transistors for next-generation displays and 3D integration applications.

In-memory computing (IMC) architectures are regarded as a promising solution for energy-efficient edge applications. However, their computational accuracy and reliability are limited by reduced signal margins, nonlinear multiply-and-accumulate (MAC) operation, power constraints, and high sensitivity to process and device-level variability. In this work, we propose a body bias (BB)-assisted optimization framework to improve the computational efficiency and robustness of SRAM-based IMC architectures. The impact of BB is first analyzed at the bitcell level, focusing on key stability and performance parameters. The analysis is then extended to different IMC architectures to evaluate the influence of BB on signal margin, MAC operation linearity, power consumption, and the number of parallel row activations, which ultimately determines the throughput of the IMC architecture. The results show that controlled BB can be effectively used as a design knob to enhance signal integrity and improve the accuracy of the MAC output. In addition, a variability analysis is performed to identify appropriate BB conditions that mitigate the impact of process variations and device-level mismatches by compensating threshold voltage fluctuations. The proposed BB-assisted approach does not require any array-level modifications and can be dynamically adapted to enable robust, reliable, and energy-efficient SRAM-based IMC design for edge computing applications. The simulation work is carried out in STMicroelectronics 28 nm Fully Depleted Silicon-On-Insulator PDK. The proposed approach achieves up to ∼9 improvement in robustness to variability, ∼75% increase in average MAC output level, and ∼4 enhancement in MAC operation throughput for SRAM-based IMC architectures.

Gallium nitride (GaN)–based normal-off high-electron-mobility transistors (HEMTs) are increasingly being explored for high-power electronics due to their capability to withstand high frequency and high breakdown voltages while maintaining reliable thermal performance. In this work, we demonstrate the effectiveness of reduced magnesium doping and gate-connected field plate integration in improving electric field distribution and device reliability. Lower magnesium acceptor doping in the p-GaN layer substantially alters the electric field distribution near the gate edge of the metal/p-GaN interface by suppressing carrier injection under strong electric field conditions. An optimal electric field peak of is achieved with the inclusion of p -GaN/p-GaN architecture. It also establishes a dual electric field control strategy by further reducing the lateral electric field from 1.73 MV cm to 1.49 MV cm with the integration of a gate-connected field plate. This synergistic effect reduces the gate leakage characteristics of the device by three orders of magnitude. As a result, p-GaN HEMTs are highly suitable for high-frequency and power conversion, as demonstrated here in a high-power boost converter, achieving an efficiency of 94.7 at a switching frequency of 10 MHz.