This work presents a comprehensive numerical investigation of bismuth oxyselenide (Bi2O2Se) as a standalone absorber material for high-efficiency single-junction solar cells using SCAPS-1D simulation. The proposed device architecture with a structure ofFTO/TiO2/Bi2O2Se/Cu2O/Ni was optimized by independently varying key material parameters, including absorber thickness, band gap, donor concentration, and defect density. Additional performance parameters were evaluated by varying the series and shunt resistances, operating temperature, and back-contact work function. Furthermore, a band alignment analysis was conducted to elucidate interfacial charge transport mechanisms and ensure a realistic device assessment. The band gap of Bi2O2Se was varied within 1.0–1.6 eV, alongsideindependent optimization of the absorber thickness, allowing precise control over the photovoltaic response. In-depth electrical analyses—comprising capacitance–voltage, Mott–Schottky characteristics, frequency-dependent capacitance, conductance response, Nyquist impedance, generation–recombination dynamics, and electron–hole current density distribution—confirmed efficient charge separation, favorable transport across the device interfaces, and suppressed recombination within the proposed device. The optimized configuration featuring a band gap of 1.4 eV and an absorber thickness of 600 nm exhibits a remarkable power conversion efficiency (PCE) of 26.03%, with JSC = 30.15 mA cm−2, VOC = 1.05 V, and fill factor = 81.63%. These results unveil Bi2O2Se as a promising next-generation absorber material with strong optoelectronic potential, offering a pathway toward efficient, stable, and environmentally benign photovoltaic technologies.

A direct coupling methodology between Geant4 and SCAPS-1D is introduced for the accurate simulation of betavoltaic devices, and validated against experimental photovoltaic measurements on GaAs/AlGaAs heterostructures. Unlike conventional approaches that rely on empirical fitting functions for the carrier generation profile, the present work computes the depth-dependent energy deposition of a 63Ni beta source directly using Geant4 with the Penelope low-energy physics constructor, converts the result to a volumetric electron–hole pair generation rate via the Klein relation, and imports it into SCAPS-1D as a user-defined profile. Six-layer and five-layer GaAs/AlGaAs n–p and p–n configurations are characterized under both AM1.5 G illumination and 63Ni irradiation. Simulated photovoltaic parameters show good agreement with experiment for both junction polarities. Under betavoltaic operation, the n–p structures maintain a consistent relative efficiency advantage of approximately 9% over the p–n structures when bulk SRH defects are present, whereas for defect-free material the polarity difference lies within the parameter-set uncertainty. Removal of the heavily doped front GaAs cap layer improves betavoltaic efficiency by 54%–62% by eliminating parasitic absorption in the surface-peaked beta deposition region. Bulk SRH defects reduce efficiency by approximately 47–53%. Shunt resistance (Rsh) is identified as a critical design parameter: at nA cm−2 current densities, Rsh ≫ 20 MΩ·cm2 is required to avoid severe fill factor degradation. Among the investigated structures, the defect-free n–p five-layer configuration achieved the highest simulated efficiency of 2.84% under 13.87 mCi cm−263Ni irradiation. A controlled sensitivity study using conventional bulk-GaAs effective densities of states (Nc = 4.21–4.70 × 1017 cm−3) confirms that the cap-removal and defect conclusions are insensitive to this parameter choice, changing the maximum efficiency only marginally (from 2.84% to 2.82%), while lowering the open-circuit voltage of the defect-containing devices by 37–40 mV. The methodology provides a physically consistent framework for heterostructure betavoltaic device design and optimization.

Understanding the origin of bias-stress instability is critical for the reliable operation of amorphous In–Ga–Zn–O (IGZO) thin-film transistors (TFTs). Here, we investigate the mechanism of positive bias stress (PBS)-induced threshold-voltage (Vth) shifts in bottom-gate IGZO TFTs through electrical, chemical, and electronic structural analyses. The devices exhibit typical n-type characteristics with a field-effect mobility of 5.2 cm2/V∙s and an on/off ratio exceeding 104. Under PBS, a significant positive Vth shift is observed, whereas the mobility and subthreshold swing remain nearly unchanged. X-ray photoelectron spectroscopy and density-of-states analyses reveal no detectable changes in the chemical states or electronic structure of the IGZO layer after PBS. In contrast, frequency-dependent capacitance measurements show a reduced resonance frequency and increased trap density in the SiO2 dielectric. These results indicate that dielectric electron trapping, rather than semiconductor degradation, is the dominant origin of PBS-induced Vth shifts in IGZO TFTs.

Contribution of ohmic contact resistance (Rc) to series resistance (Rs) was studied during the fabrication of GaAs THz Schottky barrier diodes. Ohmic contacts were characterized by cross-section TEM, EDS, backside SIMS and grazing incidence x-ray diffraction techniques, and correlated with electrical measurements. Very low contact resistances and contact resistivities (ρc) in the range of ⩽0.01 Ω·mm and 10−9 Ω·cm2, respectively, were achieved, enabling very low series resistance of 2.2 Ω and high cut-off frequencies (fT) of ∼4.5 THz. Ohmic contact formation was also simulated in a TCAD simulator. The experimentally obtained ultralow ρc values were input to the TCAD simulator to extract the I–V characteristics and Rs values which were compared with measurements to verify the self-consistency of device performance.

In this work, a low dropout voltage regulator (LDO) was designed using omega-gate nanowire transistors, following the transistor efficiency (gm/ID) design methodology. These transistors were experimentally characterized and modeled using a look-up table (LUT) approach with a Verilog-A description. The transistor model was validated by ensuring that its error remained below 1%. Based on this model, LDOs were designed to provide an output current of 100 μA and an output voltage of 1.5 V. The analysis was carried out to investigate the impact of varying gm/ID ratios from 5 V−1to 16 V−1. The improvement of error amplifier gain (AEA) for higher gm/ID results in better load regulation. At gm/ID = 16 V−1, the AEA reached 51.9 dB, yielding a load regulation of 1.62 V A−1. The open-loop gain also increased with gm/ID, achieving 82.67 dB at gm/ID = 16 V−1, which results in a power supply rejection ratio (PSR) of −80.42 dB and a line regulation of 0.09 mV V−1. On the other hand, increasing gm/ID reduces PSR bandwidth, dropping from 17 kHz at 5 V−1to 80 Hz at 16 V−1, evidencing a trade-off between PSR rate and frequency response. Under the same bias conditions, the omega-gate LDO outperformed the vertical gate-all-around nanowire-based LDO in all key performance metrics, highlighting the potential of Ω-gate nanowire transistors as an effective solution for implementing high-performance, energy-efficient LDOs in advanced semiconductor technologies.

We demonstrate first K/Ka band CW load-pull (LP) measurements of AlGaN/GaN/AlN high electron mobility transistors (HEMTs) on free-standing AlN substrates at 20GHz and above. The AlN buffer on AlN shows a much lower dislocation density compared to the same epitaxial stack grown on SiC substrates. The devices with a gate length of 220 nm exhibit an off-state leakage current below 100 µA mm−1 and a maximum Ids of around 1 A mm−1. Measured with passively-tuned LP equipment at 10 (20) GHz the devices with a gate width of 8× 75µm reveal up to 58 (40) % maximum power added efficiency, 14 (9) dB gain and 4.1 (2.8) W mm−1Pout, where higher drain voltages lead to an increase in Pout. For 30GHz 33%, 7 dB and 2.6 W mm−1 were measured with an actively-tuned equipment for 4× 50µm devices. The 20 and 30 GHz measurements are to the best of our knowledge the first reported so far for GaN HEMTs on AlN substrates underlining the potential of this material system.

We report temperature-dependent charge transport measurements in p-type high-resistivity germanium crystals grown at the University of South Dakota (USD). Hall-effect and four-probe resistivity measurements were performed on five planar samples over the temperature range 2–300 K. The Hall mobility exceeds cm V s at cryogenic temperatures and decreases systematically with increasing temperature, while the effective Hall carrier concentration exhibits strong carrier freeze-out behavior at low temperatures. The combined evolution of Hall mobility, effective Hall carrier concentration, and resistivity reveals distinct transport regimes associated with carrier freeze-out, extrinsic conduction, and increasing lattice-scattering influence. The transport behavior is interpreted within a Matthiessen’s-rule-inspired phenomenological mobility model, motivated by the expected temperature dependences of impurity- and lattice-scattering processes. The temperature dependence of the mobility is captured by an effective exponent – depending on the sample, spanning values both below and above the expected for acoustic-phonon-limited transport; the limited temperature sampling does not permit a unique identification of individual lattice-scattering mechanisms. Variations among samples are correlated with differences in effective Hall carrier concentration and transport behavior, although the samples span a factor of five in thickness and bulk impurity effects therefore cannot be uniquely separated from thickness-dependent surface, contact, and processing contributions. These measurements establish a transport baseline for high-resistivity germanium crystals grown at the USD and provide guidance for future material optimization toward detector-grade high-purity germanium for low-background rare-event detector applications.

This study investigates the dynamic negative bias temperature instability (NBTI) in PMOS field-effect transistors (FETs) across a temperature range of 77–370 K. PMOS-FETs with varying gate oxide thicknesses are widely employed in integrated circuits. Here, we examine the degradation mechanisms underlying NBTI by analyzing the influence of gate oxide thickness and temperature conditions. Our findings reveal that conventional degradation models fail to adequately explain the non-Arrhenius behavior of NBTI observed at low temperatures. To address this, we propose a mechanism that incorporates both the capture and release dynamics of interface traps (Nit) and oxide traps (Not), highlighting their distinct roles at 77 K. Specifically, we identify that Not dominates in thin-gate oxides at low temperatures, whereas both Nit and Not contribute significantly in thick-gate oxides. Furthermore, the observed behavior at lower temperatures and in thinner gate oxides is qualitatively consistent with the non-radiative multiphonon framework, particularly with respect to charge trapping under reduced thermal activation. At higher temperatures and in thicker oxides, the experimental trends may also be interpreted as involving a possible contribution from gate-side hydrogen release, including hydrogen-related trap formation and field-assisted transport. These results provide a physically grounded framework for interpreting NBTI behavior in PMOS-FETs across a wide temperature range by clarifying the distinct contributions associated with oxide thickness and temperature.

This article analyses the effects of lateral straggling and interface trap on the characteristics of SOI TFETs with an n–p–n configuration in double gate structures using TCAD simulation. The study considers the effects of lateral straggle ( ) in both source and drain regions, along with the impact of acceptor-like and donor-like interface traps having Gaussian distribution. Key analog and RF performance metrics, such as transconductance efficiency ( ), total gate capacitance ( ), gate-to-source capacitance ( ), and gate-to-drain capacitance ( ), cut-off frequency ( ), and intrinsic delay ( under analytical doping profiles are reported. The findings indicate that source-side straggle substantially impairs device performance by widening the tunneling barrier, resulting in diminished and increased , especially at greater σ values. On the other hand, drain-side straggle mostly raises because of stronger coupling, especially in the ambipolar region. The acceptor-like traps lower the performance of the device due to their effect on lowering the carrier density and tunneling rate, while donor-like traps enhance the local electric field intensity, thus increasing the drain current. Based on sensitivity analysis, traps play a critical role within the subthreshold regime. Overall, the work offers insights into the effects of lateral straggle of dopants and interface traps through DC and RF analysis.

In gate-all-around (GAA) nanosheet field-effect transistors, a higher dielectric constant produces a larger physical high- thickness for a given equivalent oxide thickness, lowering direct tunnelling across the gate that wraps each stacked sheet. This work evaluates 35 gate-dielectric compositions in a four-stack GAA nanosheet FET. Density functional theory-derived dielectric constants ( ) for SiO /SiON/HfO references, doped HfO oxides, and HfMON oxynitrides (M = Al, La, Sr, Ba) were translated into technology computer-aided design material inputs. Across the 35-material set, the intrinsic direct-tunnelling on-state gate current ( ) varies by 15.2 decades, drain-induced barrier lowering varies from 30.8 to 64.6 mV V , and on-state drain current ( ) varies by 9.5%. The latter range is smaller than the change produced by a eV metal-gate work-function shift and illustrates the sensitivity of drive current to gate work function. HfLaON (9% La, 6% N) reduces by 10.3 decades from the HfO value while changing by only 0.20%. The reported values are intrinsic direct-tunnelling estimates. Process-dependent trap conduction can limit the practical leakage reduction.